One solution for interconnecting chips that are stacked on top of one another consists in using the vertical faces of the stack, which are metallized, to form the electrical connections between chips. These chips include connection pads that are connected to connection bumps, but do not include electrical bonding wires leading from these pads. Such a solution, which is also referred to as WDoD technology, is described in the patents FR 2 857 157 (inventors: Val Christian and Lignier Olivier) and FR 2 905 198 (inventor: Val Christian). However, it is expensive to implement.
One less expensive solution consists in using chip-on-chip (CoC) technology, using stacked and wired chips. One example of a 3D electronic module obtained using this technology is shown in FIG. 1 with two chips 1 stacked on an interconnect substrate 2 such as a PCB (printed circuit board). It can be seen that regularly wired wire ribbons 15 link the pads 10 of each chip 1 to the solder bumps 30 of the substrate 2 to which the first chip is bonded, the second chip being bonded to the first.
Stacking chips using chip-on-chip (CoC) technology is to this day one of the densest and most commonly used techniques in the world (e.g. in phones, etc.). The stacked chips 1 include connection pads 10 and electrical bonding wires 15 leading from these pads.
However, the “footprint” or horizontal area (i.e. area in a plane x,y that is perpendicular to the direction z of the stack) taken up by a stack obtained using this CoC technology is generally twice as large as that obtained using WDoD technology. Chips of variable size, having horizontal areas that are typically comprised between 6×6 mm2 for small chips and 9×9 mm2 for large chips, are generally stacked on an interconnect circuit 2 for interconnecting the stack with another, external circuit by means of connection bumps. In the case of a stack of chips having variable areas, they are stacked in order of decreasing area (the largest chip is at the bottom of the stack on the PCB, and the smallest chip is at the top of the stack).
The solder bumps 30 on the carrier substrate take up a substantial amount of space. It is estimated that, at these solder bumps, the distance between each wire ribbon varies from 400 μm to 800 μm, i.e. 500 μm on average. For four stacked chips, a distance of 4×500 μm=2000 μm=2 mm around the stack is obtained, i.e. for the stack provided with these electrical bonding wires, a horizontal area of:                (6 mm+(2×2 mm))×(6 mm+(2×2 mm))=100 mm2 for a stack of four small chips, while, using WDoD, there is 100 μm around the chips, which gives an area of 6.2×6.2=38.5 mm2, namely 2.5 times smaller than the area using CoC technology and        (9 mm+(2×2 mm))×(9 mm+(2×2 mm))=169 mm2 for a stack of four chips with at least one large chip, while WDoD gives an area of 9.2×9.2=84.6 mm2, namely 2 times smaller than the area using CoC technology.        
Furthermore, the length of the bonding wires varies from 1 to 3 mm between the ribbon that is closest to the chip and the ribbon that is furthest away therefrom.
The {stack with PCB—wires bonded to the substrate} assembly is next overmolded with resin, then diced to obtain a 3D electronic module ready to be delivered to a manufacturer.
Additionally, a problem of signal integrity occurs when the stack includes chips operating in the microwave frequency domain, in particular beyond 2 GHz.
Consequently, there still remains a need for a process for interconnecting stacked chips that simultaneously meets all of the aforementioned needs in terms of fabrication cost, “footprint” and signal integrity at microwave frequencies.